62.5mhz to 250mhz, 1-to-4 lvcmos/ lvttl zero delay clock buffer ICS86004-02 idt ? / ics ? lvcmos/lvttl zero delay clock buffer 1 ics86004ag-02 rev a november 3, 2006 preliminary g eneral d escription the ICS86004-02 is a high performance 1-to-4 lvcmos/lvttl clock buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the ICS86004-02 has a fully integrated pll and can be configured as zero delay buffer and has an input and output frequency range of 62.5mhz to 250mhz. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clocks. the pll_sel pin can be used to bypass the pll for system test and debug purposes. in bypass mode, the refer- ence clock is routed around the pll and into the internal out- put divider. ICS86004-02 has a special feature that when clk is lost, it will disable the output to logic low. f eatures four lvcmos/lvttl outputs, 7 ? typical output impedance single lvcmos/lvttl clock input clk accepts the following input levels: lvcmos or lvttl output frequency range: 62.5mhz to 250mhz input frequency range: 62.5mhz to 250mhz external feedback for ?zero delay? clock regeneration with configurable frequencies fully integrated pll cycle-to-cycle jitter, (f_sel = 1): 35ps (typical) output skew: 45ps (typical) supply voltage modes: (core/output) 3.3v/3.3v 3.3v/2.5v 5v tolerant input 0c to 70c ambient operating temperature available in both standard (rohs 5) and lead-free (rohs 6) compliant packages hiperclocks? ic s b lock d iagram p in a ssignment pll_sel clk fb_in mr f_sel q0 q1 q2 q3 q1 gnd q0 f_sel v dd clk gnd v dda 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v ddo q2 gnd q3 v ddo mr fb_in pll_sel ICS86004-02 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view c ontrol i nput f unction t able t u p n i t u p t u o / t u p n i ) z h m ( e g n a r y c n e u q e r f l e s _ fm u m i n i mm u m i x a m 05 2 10 5 2 15 . 2 65 2 1 pll 1:1 8 0 1 0 1 loss reference detect pulldown pulldown pulldown pulldown pullup the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 2 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d , 3 , 1 5 1 , 3 1 , 0 q , 1 q 2 q , 3 q t u p t u o7 . s t u p t u o k c o l c ? . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e c n a d e p m i t u p t u o l a c i p y t 4 1 , 7 , 2d n gr e w o p. d n u o r g y l p p u s r e w o p 4l e s _ ft u p n in w o d l l u p m o r f s i e g n a r y c n e u q e r f o / i , w o l n e h w . t u p n i t c e l e s e g n a r y c n e u q e r f m o r f s i e g n a r y c n e u q e r f o / i , h g i h n e h w . z m 0 5 2 o t z h m 5 2 1 . s l e v e l e c a f r e t n i l t t v l / s o m c v l . z h m 5 2 1 o t z h m 5 . 2 6 5v d d r e w o p. n i p y l p p u s e r o c 6k l ct u p n in w o d l l u p. t u p n i k c o l c l t t v l / s o m c v l 8v a d d r e w o p. n i p y l p p u s g o l a n a 9l e s _ l l pt u p n ip u l l u p . s r e d i v i d e h t o t t u p n i s a k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s , h g i h n e h w . ) s s a p y b l l p ( k c o l c e c n e r e f e r e h t s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l . ) d e l b a n e l l p ( l l p s t c e l e s 0 1n i _ b ft u p n in w o d l l u p . " y a l e d o r e z " h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o e h t f o e n o o t t c e n n o c 1 1r mt u p n in w o d l l u p t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . w o l o g o t s t u p t u o e h t g n i s u a c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o 6 1 , 2 1v o d d r e w o p. s n i p y l p p u s t u p t u o : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3. c ontrol i nput f unction t able t u p n i t u p t u o / t u p n i ) z h m ( e g n a r y c n e u q e r f l e s _ fm u m i n i mm u m i x a m 05 2 10 5 2 15 . 2 65 2 1 l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v , a d d v , o d d v 5 6 4 . 3 =d b tf p v d d v , a d d , v 5 6 4 . 3 = v o d d v 5 2 6 . 2 = d b tf p r t u o e c n a d e p m i t u p t u o% 5 v 3 . 3572 1 ?
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 3 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = -0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 3 1 . 0 ?3 . 3v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 5 8a m i a d d t n e r r u c y l p p u s g o l a n a 3 1a m i o d d t n e r r u c y l p p u s t u p t u o 4a m a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 89c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4b. p ower s upply dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 3 1 . 0 ?3 . 3v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 5 8a m i a d d t n e r r u c y l p p u s g o l a n a 3 1a m i o d d t n e r r u c y l p p u s t u p t u o 4a m t able 4c. lvcmos / lvttl dc c haracteristics , t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n iv d d v 3 . 3 =2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n iv d d v 3 . 3 =3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , r m , k l c l e s _ f , n i _ b f v d d v = n i v 5 6 4 . 3 =0 5 1a l e s _ l l pv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i , r m , k l c l e s _ f , n i _ b f v d d v , v 5 6 4 . 3 = n i v 0 =5 -a l e s _ l l pv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o v o d d v 5 6 4 . 3 =6 . 2v v o d d v 5 2 6 . 2 =8 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o d d v 5 2 6 . 2 r o v 5 6 4 . 3 =5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o d d , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . s m a r g a i d t i u c r i c t s e t d a o l t u p t u o
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 4 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary t able 5a. ac c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 = l e s _ f5 2 10 5 2z h m 1 = l e s _ f5 . 2 65 2 1z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p , v 0 = l e s _ l l p e d o m s s a p y b 8 . 5s n ) ? ( t4 , 2 e t o n ; t e s f f o e s a h p c i t a t sv 3 . 3 = l e s _ l l p0 3 3s p t ) o ( k s4 , 3 e t o n ; w e k s t u p t u ov 0 = l e s _ l l p0 6s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 = l e s _ f0 4s p 1 = l e s _ f5 3s p t l e m i t k c o l l l p 1s m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 5s p c d oe l c y c y t u d t u p t u o 0 = l e s _ f0 5% 1 = l e s _ f0 5% t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n v o d d . 2 / e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n l a n g i s t u p n i k c a b d e e f e g a r e v a . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 5b. ac c haracteristics , v dd = v dda = 3.3v5%, v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 = l e s _ f5 2 10 5 2z h m 1 = l e s _ f5 . 2 65 2 1z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p , v 0 = l e s _ l l p e d o m s s a p y b 2 . 6s n ) ? ( t4 , 2 e t o n ; t e s f f o e s a h p c i t a t sv 3 . 3 = l e s _ l l p5 8 2s p t ) o ( k s4 , 3 e t o n ; w e k s t u p t u ov 0 = l e s _ l l p5 4s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 = l e s _ f5 4s p 1 = l e s _ f5 3s p t l e m i t k c o l l l p 1s m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 5s p c d oe l c y c y t u d t u p t u o 0 = l e s _ f0 5% 1 = l e s _ f0 5% t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n v o d d . 2 / e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n l a n g i s t u p n i k c a b d e e f e g a r e v a . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 5 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary 3.3v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v5% -1.65v5% scope qx gnd lvcmos 1.25v5% -1.25v5% c ycle - to -c ycle j itter o utput s kew t jit(cc) = t cycle n ? t cycle n+1 1000 cycles q0:q3 ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t sk(o) v ddo 2 v ddo 2 qy qx o utput d uty c ycle /p ulse w idth /p eriod (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset ? ? t (?) v dd 2 v dd 2 clk fb_in p arameter m easurement i nformation v dd , v ddo v dd s tatic p hase o ffset v ddo 2.05v5% t pw t period v ddo 2 v ddo 2 v ddo 2 t pw t period odc = q0:q3 p ropagation d elay o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f q0:q3 tp lh tp hl v ddo 2 v dd 2 v ddo 2 v dd 2 clk v dda 2.05v5% 1.65v5% v dda
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 6 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS86004-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 ? resistor along with a 10f and a .01 f bypass capacitor should be connected to each v dda . the 10 ? resistor cn also be replaced by a ferrite bead. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 ? v dda 10 f .01 f 3.3v .01 f v dd i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. there should be no trace attached.
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 7 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary r eliability i nformation t ransistor c ount the transistor count for ICS86004-02 is: 2782 t able 6. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 8 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary p ackage o utline - g s uffix for 16 l ead tssop t able 7. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? lvcmos/lvttl zero delay clock buffer 9 ics86004ag-02 rev a november 3, 2006 ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 2 0 - g a 4 0 0 6 8 s c i2 0 a 4 0 0 6 8p o s s t d a e l 6 1e b u tc 0 7 o t c 0 t 2 0 - g a 4 0 0 6 8 s c i2 0 a 4 0 0 6 8p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 2 0 - g a 4 0 0 6 8 s c id b tp o s s t " e e r f - d a e l " d a e l 6 1e b u tc 0 7 o t c 0 t f l 2 0 - g a 4 0 0 6 8 s c id b tp o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS86004-02 62.5mhz to 250mhz, 1-to-4 lvcmos/lvttl zero delay clock buffer preliminary
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